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Assertion Based Verification (ABV) is a methodology employing assertions as the primary entry for verification, potentially both employing the assertions for simulation as well as formal property checking. ABV significantly improves the efficiency of the verification effort. Today the SystemVerilog Assertion language (SVA) is the state-of-art for employing ABV


Constrained Random Verification is a methodology that takes full advantage of verification environment automation and it dramatically reduces the time spent for creating test cases. Comparing this with the classical directed test creation approach, CRV significantly improves the RTL quality by easily hitting corner cases and finding unexpected bugs. The SystemVerilog methodologies VMM and OVM are today the industry standard for employing CRV.


Verification Interllectual Property (VIP) is a methodology for efficiently creating and reusing test bench structures aimed for CRV. Typically, SystemVerilog based VIP is implemented to be used with the VMM and OVM methodologies.

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