SyoSil to present at OVM World, DAC 200921. July. 2009
Come meet us at OVM World at the upcoming DAC 2009 in San Francisco. We'll be presenting at Thu July 30th at booth #3450, at 9am.
For more information:
The abstract of the presentation:
Decoupling OVM Test Bench Design from the RTL Development Schedule: Standalone Design & Verification of OVCs
Abstract: While offering numerous new items for the verification engineer toolbox, OVM and SystemVerilog also challenges the engineer with a significant learning curve and an increased amount of complexity in the areas of languages, tools and methodologies, something that initially threatens to lower the engineer productivity. To address these challenges, it is of great importance to be able to employ a high degree of reusability of verification components, a concept also known as Verification IP (VIP). Today the OVM methodology offers a well documented VIP concept, namely the Open Verification Components (OVCs). This concept successfully addresses VIP modularity, connectivity and reusability. As an extension to the OVCs, this presentation introduces an industry-proven, first-timeright standardized methodology of designing, verifying and documenting OVCs, while being independent of the RTL development schedule. By focusing on OVC common look and feel, the methodology aims for an increased productivity for both the OVC implementer and user. Even for complex industry-standard protocols, OVC authors know exactly what to write, and OVC users know exactly what features to expect and how to invoke them. The presentation describes a well documented approach of how to verify the OVC in a stand-alone context, including a precise sign-off criteria. The approach decouples the OVC development from any RTL design development effort, and ensures that even very complex OVCs are fully verified before being employed in an RTL test bench. This eliminates the scenario of having functional errors in the OVC that cloak errors in the RTL, which greatly enhances verification engineer productivity and the general quality outcome of the verification process. Actual industry experience shows that this methodology allows the engineer using the OVCs to focus on the actual RTL without having to search for bugs in the OVC. Most importantly, the methodology allows the OVM VIP and TB development task to be largely absent from the critical RTL development schedule, as the verification components and environments can be created and verified in advance or in parallel to the RTL development, leading to an overall positive project schedule impact.
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