OVM_SYO Based Verification
Do you want to become productive using OVM 2.0 for creating Verification IP (VIP) and Constrained-Random test benches, in a record-breaking short time? SyoSil will teach you how to:
- Employ a methodology, which designs and verifies OVM VIP first-time-right, avoiding long hours debugging complex test cases, not knowing if the bug is in your RTL block or in your test bench.
- Efficiently decouple the development of your OVM VIP and test bench from the time critical path of your project.
- Get a highly skilled verification team working with OVM VIP and test benches in a uniform manner, where everybody knows what to implement and what to expect from OVM VIP.
Layered Approach to OVM
Based on our year-long SystemVerilog expertise, SyoSil has created the OVM_SYO methodology and the OVM_SYO library on the top of OVM 2.0. This ensures that OVM VIP, test benches and test cases are created in a uniform and reusable manner. Full OVM compatibility is still preserved while using the OVM_SYO methodology.
Protocols are by nature quite different. Some are simple master/slave protocols, whereas some are highly pipelined multi-point protocols with independent address and data phases and using tagged transfers. Experience from industry applications has shown that the OVM_SYO concept addresses both simple and complex protocols.
OVM_SYO Based Verification Component (OVC)
In addition to creating OVCs as described in the OVM 2.0 documentation, SyoSil has set internal standards of how verification components are written. Using the OVM_SYO guidelines in the OVM_SYO framework ensures that your OVCs offer following advantages:
- A common look and feel: OVC authors know exactly what to write, and OVC users know exactly what features to expect and how to invoke them.
- Stand-alone verification of OVCs, which enables OVC development independently of availability and state of any RTL block using the same protocol.
- Easy and standardized reuse based integration of multiple OVCs in test benches scaling from block to system level.
OVM_SYO based OVCs are verified in a stand-alone context. Protocol compliance is ensured, independently of the availability of any RTL models, and the mirroring of any RTL protocol bugs is avoided. The OVC and test bench creation phase is removed from the critical path of the design and verification development cycle.
OVM_SYO based OVCs always implement both sides of the protocol (e.g. master and slave). This allows the complete OVC to be verified against it self by running both directed and random stimuli over a DUT interface connecting the two instances of the OVC. Protocol assertions serve as a reference model, checking that the BFM correctly implements the protocol. The generic SyoSil scoreboard architecture is attached, verifying that the requestor, the responder and the passive (monitor) OVCs all have the same understanding of valid transactions on the interface.
With a single requirement, having the RTL interface ready, OVCs can be developed prior to RTL being available. This allows completing the OVC and test bench development before or simultaneously with the RTL. The OVM_SYO methodology simply removes the OVC and test bench creation from being in the critical path of the design and verification development cycle.
OVC Based Test Benches
OVM_SYO prescribes a methodology for building test benches based on OVC reuse, guaranteeing easy debug-able test bench implementations with small foot prints. Using the built-in OVM_SYO Utilities gives a generic scoreboard and reference model architecture, and the methodology is fully scalable from block to system level.
Test benches built accordingly to OVM_SYO features:
- Full OVM 2.0 Compliance
- Scales from block to system level verification
- Randomization of HW and SW configurations
- Generic scoreboard architecture
- Reference models with OVM_SYO base class support for modeling of control and status registers.
For more information related to the OVM_SYO based OVC development and related services, please contact us with your request.