VMM_SYO Based Verification
SyoSil introduces an industry-proven, standardized way of writing VMM compliant Verification IP (VIP), namely the concept of SystemVerilog Verification Components (SVVCs). This concept gives a superior engineering productivity, which in turn leads to finding more RTL design bugs, as the verification engineer ultimately is able to focus on the device, rather than spending time on debugging a complex hard-to-understand verification environment.
SyoSil offers methodology consulting services, aiming at implementing and adapting the SVVC concept in order to improve the verification productivity and reusability. By employing the SVVC concept to build VIP and test benches, the chance of first-time silicon pass using VMM is greatly enhanced.
Layered Approach to VMM
Based on our year-long SystemVerilog expertise, SyoSil has created a set of generic SystemVerilog utilities. Together with a set of base classes built on the top of VMM, namely the VMM_SYO framework, a unique platform has been built. This platform ensures that SVVCs, test benches and test cases are created in a uniform and reusable manner, keeping down the footprint of the actual user written code, while still preserving full VMM compatibility.
The SystemVerilog Verification Component (SVVC)
The SystemVerilog Verification Component (SVVC) concept has been developed by SyoSil to standardize how VMM compliant VIP is built across protocols. Using the SVVC concept instead of writing VMM VIP in any arbitrary form or structure offers following advantages:
Protocols are by nature quite different. Some are simple master/slave protocols, whereas some are highly pipelined multi-point protocols with independent address and data phases and using tagged transfers. Experience from industry applications has shown that the SVVC concept addresses both simple and complex protocols.
- Proven support for constrained random verification and directed testing.
- A common look and feel: SVVC authors know exactly what to write, and SVVC users know exactly what features to expect and how to invoke them.
- Stand-alone verification of the SVVC, which enables development of the SVVC, independently of the availability and state of any RTL block using the same protocol.
- Easy and standardized reuse based integration of multiple SVVCs in test benches scaling from block to system level.
The following components exist by default in an SVVC:
- agen: atomic random generator
- sgen: sequence random generator
- other gen: other generator(s)
- dtst: direct test generator
- bfm: requestor or responder
- bro: broker
- mon: monitor, passive
- brc: broadcaster
- cov: stimuli functional coverage
- cfg: SVVC configuration
When using VMM_SYO, SVVCs are verified in a stand-alone context. Protocol compliance is ensured, independently of the availability of any RTL models, and the mirroring of any RTL protocol bugs is avoided. The SVVC and test bench creation phase is removed from the critical path of the design and verification development cycle.
An SVVC always implements both sides of the protocol (e.g. master and slave). This allows the complete SVVC to be verified against itself by running both directed and random stimuli over a DUT interface connecting the two instances of the SVVCs. Protocol assertions serves as a reference model, checking that the protocol is correctly implemented by the BFM. The generic SyoSil scoreboard architecture is attached, verifying that both the requestor BFM, the responder BFM and the passive BFM (monitor) all have the same understanding of valid transactions on the interface.
SVVC Based Test Benches
VMM_SYO prescribes a methodology for building test benches based on SVVC reuse, guaranteeing easy debug-able test bench implementations with small foot prints.
Test benches built accordingly to VMM_SYO features:
- Scales from block to system level verification
- Single-file organized test cases
- Randomization and DUT application of hardware and software configurations
- Two-pass mechanism enabling randomization of elaborated RTL configuration
- Generic scoreboard architecture using generic compare method on any number of queues
- Easily modeled transaction-level reference models with VMM_SYO base class support for modeling of control and status registers.
- Automated, pre-coded control and status register verification suites
For more information related to the VMM_SYO based SVVC development and related services, please contact us with your request.